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Figure 14.6. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation
ADDRSETUP
(1, 2, 3, ...)
ADDRHOLD
(0, 1, 2, ...)
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
EBI_AD[ 15:0]
ADDR[ 15:0]
DATA[ 15:0]
Z
EBI_ALE
EBI_CSn
EBI_WEn
14.3.3 24-bit Address Mode
This mode allows 24-bit address with 8-bit data multiplexed on the EBI_AD lines. The upper 8 bits of
the EBI_AD lines are consecutively used for the highest 8 bits and the lowest 8 bits of the address. The
lower 8 bits of the EBI_AD lines are used for the middle 8 address bits and for data. This mode is set
by programming the MODE field in the EBI_CTRL register to D8A24ALE. Read and write signals are
shown in Figure 14.7 (p. 137) and Figure 14.8 (p. 137) respectively.
Figure 14.7. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation
ADDRSETUP
(1, 2, 3, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_AD[ 15:8]
ADDR[ 23:16]
ADDR[ 7:0]
Z
EBI_AD[ 7:0]
ADDR[ 15:8]
Z
DATA[ 7:0]
Z
EBI_ALE
EBI_CSn
EBI_REn
Figure 14.8. EBI Multiplexed 8-bit Data, 24-bit Address Write Operation
EBI_AD[ 15:8]
EBI_AD[ 7:0]
ADDRSETUP
(1, 2, 3, ...)
ADDR[ 23:16]
ADDR[ 15:8]
ADDRHOLD
(0, 1, 2, ...)
WRSETUP
(0, 1, 2, ...)
ADDR[ 7:0]
DATA[ 7:0]
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
Z
Z
EBI_ALE
EBI_CSn
EBI_WEn
14.3.4 Timing
The duration of the states in the transaction is defined by the corresponding uppercase name above
the state, e.g. the address setup state in Figure 14.8 (p. 137) is active for a number of internal clock
cycles defined by ADDRSET bitfield in the EBI_ADDRTIMING register. Similar timing can be defined
by the RDSTRB bitfield in the EBI_RDTIMING register and WRSTRB in the EBI_WRTIMING register.
These parameters all have a minimum duration of 1 cycle, which is set by HW, and writing a value n to
any of these bitfields results in an extended duration of 1+n cycles.
2011-04-12 - d0001_Rev1.10
137
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